src/video/fbcon/riva_mmio.h
author Edgar Simo <bobbens@gmail.com>
Sun, 06 Jul 2008 17:06:37 +0000
branchgsoc2008_force_feedback
changeset 2498 ab567bd667bf
parent 1895 c121d94672cb
permissions -rw-r--r--
Fixed various mistakes in the doxygen.
     1 /***************************************************************************\
     2 |*                                                                           *|
     3 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
     4 |*                                                                           *|
     5 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
     6 |*     international laws.  Users and possessors of this source code are     *|
     7 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
     8 |*     use this code in individual and commercial software.                  *|
     9 |*                                                                           *|
    10 |*     Any use of this source code must include,  in the user documenta-     *|
    11 |*     tion and  internal comments to the code,  notices to the end user     *|
    12 |*     as follows:                                                           *|
    13 |*                                                                           *|
    14 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
    15 |*                                                                           *|
    16 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
    17 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
    18 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
    19 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
    20 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
    21 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
    22 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
    23 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
    24 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
    25 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
    26 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
    27 |*                                                                           *|
    28 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
    29 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
    30 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
    31 |*     computer  software  documentation,"  as such  terms  are  used in     *|
    32 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
    33 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
    34 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
    35 |*     all U.S. Government End Users  acquire the source code  with only     *|
    36 |*     those rights set forth herein.                                        *|
    37 |*                                                                           *|
    38 \***************************************************************************/
    39 
    40 #ifndef __RIVA_HW_H__
    41 #define __RIVA_HW_H__
    42 #define RIVA_SW_VERSION 0x00010003
    43 
    44 /*
    45  * Typedefs to force certain sized values.
    46  */
    47 typedef Uint8 U008;
    48 typedef Uint16 U016;
    49 typedef Uint32 U032;
    50 
    51 /*
    52  * HW access macros.
    53  */
    54 #define NV_WR08(p,i,d)  (((U008 *)(p))[i]=(d))
    55 #define NV_RD08(p,i)    (((U008 *)(p))[i])
    56 #define NV_WR16(p,i,d)  (((U016 *)(p))[(i)/2]=(d))
    57 #define NV_RD16(p,i)    (((U016 *)(p))[(i)/2])
    58 #define NV_WR32(p,i,d)  (((U032 *)(p))[(i)/4]=(d))
    59 #define NV_RD32(p,i)    (((U032 *)(p))[(i)/4])
    60 #define VGA_WR08(p,i,d) NV_WR08(p,i,d)
    61 #define VGA_RD08(p,i)   NV_RD08(p,i)
    62 
    63 /*
    64  * Define supported architectures.
    65  */
    66 #define NV_ARCH_03  0x03
    67 #define NV_ARCH_04  0x04
    68 #define NV_ARCH_10  0x10
    69 /***************************************************************************\
    70 *                                                                           *
    71 *                             FIFO registers.                               *
    72 *                                                                           *
    73 \***************************************************************************/
    74 
    75 /*
    76  * Raster OPeration. Windows style ROP3.
    77  */
    78 typedef volatile struct
    79 {
    80     U032 reserved00[4];
    81     U016 FifoFree;
    82     U016 Nop;
    83     U032 reserved01[0x0BB];
    84     U032 Rop3;
    85 } RivaRop;
    86 /*
    87  * 8X8 Monochrome pattern.
    88  */
    89 typedef volatile struct
    90 {
    91     U032 reserved00[4];
    92     U016 FifoFree;
    93     U016 Nop;
    94     U032 reserved01[0x0BD];
    95     U032 Shape;
    96     U032 reserved03[0x001];
    97     U032 Color0;
    98     U032 Color1;
    99     U032 Monochrome[2];
   100 } RivaPattern;
   101 /*
   102  * Scissor clip rectangle.
   103  */
   104 typedef volatile struct
   105 {
   106     U032 reserved00[4];
   107     U016 FifoFree;
   108     U016 Nop;
   109     U032 reserved01[0x0BB];
   110     U032 TopLeft;
   111     U032 WidthHeight;
   112 } RivaClip;
   113 /*
   114  * 2D filled rectangle.
   115  */
   116 typedef volatile struct
   117 {
   118     U032 reserved00[4];
   119     U016 FifoFree;
   120     U016 Nop[1];
   121     U032 reserved01[0x0BC];
   122     U032 Color;
   123     U032 reserved03[0x03E];
   124     U032 TopLeft;
   125     U032 WidthHeight;
   126 } RivaRectangle;
   127 /*
   128  * 2D screen-screen BLT.
   129  */
   130 typedef volatile struct
   131 {
   132     U032 reserved00[4];
   133     U016 FifoFree;
   134     U016 Nop;
   135     U032 reserved01[0x0BB];
   136     U032 TopLeftSrc;
   137     U032 TopLeftDst;
   138     U032 WidthHeight;
   139 } RivaScreenBlt;
   140 /*
   141  * 2D pixel BLT.
   142  */
   143 typedef volatile struct
   144 {
   145     U032 reserved00[4];
   146     U016 FifoFree;
   147     U016 Nop[1];
   148     U032 reserved01[0x0BC];
   149     U032 TopLeft;
   150     U032 WidthHeight;
   151     U032 WidthHeightIn;
   152     U032 reserved02[0x03C];
   153     U032 Pixels;
   154 } RivaPixmap;
   155 /*
   156  * Filled rectangle combined with monochrome expand.  Useful for glyphs.
   157  */
   158 typedef volatile struct
   159 {
   160     U032 reserved00[4];
   161     U016 FifoFree;
   162     U016 Nop;
   163     U032 reserved01[0x0BB];
   164     U032 reserved03[(0x040) - 1];
   165     U032 Color1A;
   166     struct
   167     {
   168         U032 TopLeft;
   169         U032 WidthHeight;
   170     } UnclippedRectangle[64];
   171     U032 reserved04[(0x080) - 3];
   172     struct
   173     {
   174         U032 TopLeft;
   175         U032 BottomRight;
   176     } ClipB;
   177     U032 Color1B;
   178     struct
   179     {
   180         U032 TopLeft;
   181         U032 BottomRight;
   182     } ClippedRectangle[64];
   183     U032 reserved05[(0x080) - 5];
   184     struct
   185     {
   186         U032 TopLeft;
   187         U032 BottomRight;
   188     } ClipC;
   189     U032 Color1C;
   190     U032 WidthHeightC;
   191     U032 PointC;
   192     U032 MonochromeData1C;
   193     U032 reserved06[(0x080) + 121];
   194     struct
   195     {
   196         U032 TopLeft;
   197         U032 BottomRight;
   198     } ClipD;
   199     U032 Color1D;
   200     U032 WidthHeightInD;
   201     U032 WidthHeightOutD;
   202     U032 PointD;
   203     U032 MonochromeData1D;
   204     U032 reserved07[(0x080) + 120];
   205     struct
   206     {
   207         U032 TopLeft;
   208         U032 BottomRight;
   209     } ClipE;
   210     U032 Color0E;
   211     U032 Color1E;
   212     U032 WidthHeightInE;
   213     U032 WidthHeightOutE;
   214     U032 PointE;
   215     U032 MonochromeData01E;
   216 } RivaBitmap;
   217 /*
   218  * 3D textured, Z buffered triangle.
   219  */
   220 typedef volatile struct
   221 {
   222     U032 reserved00[4];
   223     U016 FifoFree;
   224     U016 Nop;
   225     U032 reserved01[0x0BC];
   226     U032 TextureOffset;
   227     U032 TextureFormat;
   228     U032 TextureFilter;
   229     U032 FogColor;
   230 /* This is a problem on LynxOS */
   231 #ifdef Control
   232 #undef Control
   233 #endif
   234     U032 Control;
   235     U032 AlphaTest;
   236     U032 reserved02[0x339];
   237     U032 FogAndIndex;
   238     U032 Color;
   239     float ScreenX;
   240     float ScreenY;
   241     float ScreenZ;
   242     float EyeM;
   243     float TextureS;
   244     float TextureT;
   245 } RivaTexturedTriangle03;
   246 typedef volatile struct
   247 {
   248     U032 reserved00[4];
   249     U016 FifoFree;
   250     U016 Nop;
   251     U032 reserved01[0x0BB];
   252     U032 ColorKey;
   253     U032 TextureOffset;
   254     U032 TextureFormat;
   255     U032 TextureFilter;
   256     U032 Blend;
   257 /* This is a problem on LynxOS */
   258 #ifdef Control
   259 #undef Control
   260 #endif
   261     U032 Control;
   262     U032 FogColor;
   263     U032 reserved02[0x39];
   264     struct
   265     {
   266         float ScreenX;
   267         float ScreenY;
   268         float ScreenZ;
   269         float EyeM;
   270         U032 Color;
   271         U032 Specular;
   272         float TextureS;
   273         float TextureT;
   274     } Vertex[16];
   275     U032 DrawTriangle3D;
   276 } RivaTexturedTriangle05;
   277 /*
   278  * 2D line.
   279  */
   280 typedef volatile struct
   281 {
   282     U032 reserved00[4];
   283     U016 FifoFree;
   284     U016 Nop[1];
   285     U032 reserved01[0x0BC];
   286     U032 Color;                 /* source color               0304-0307 */
   287     U032 Reserved02[0x03e];
   288     struct
   289     {                           /* start aliased methods in array   0400-    */
   290         U032 point0;            /* y_x S16_S16 in pixels            0-   3 */
   291         U032 point1;            /* y_x S16_S16 in pixels            4-   7 */
   292     } Lin[16];                  /* end of aliased methods in array      -047f */
   293     struct
   294     {                           /* start aliased methods in array   0480-    */
   295         U032 point0X;           /* in pixels, 0 at left                0-   3 */
   296         U032 point0Y;           /* in pixels, 0 at top                 4-   7 */
   297         U032 point1X;           /* in pixels, 0 at left                8-   b */
   298         U032 point1Y;           /* in pixels, 0 at top                 c-   f */
   299     } Lin32[8];                 /* end of aliased methods in array      -04ff */
   300     U032 PolyLin[32];           /* y_x S16_S16 in pixels         0500-057f */
   301     struct
   302     {                           /* start aliased methods in array   0580-    */
   303         U032 x;                 /* in pixels, 0 at left                0-   3 */
   304         U032 y;                 /* in pixels, 0 at top                 4-   7 */
   305     } PolyLin32[16];            /* end of aliased methods in array      -05ff */
   306     struct
   307     {                           /* start aliased methods in array   0600-    */
   308         U032 color;             /* source color                     0-   3 */
   309         U032 point;             /* y_x S16_S16 in pixels            4-   7 */
   310     } ColorPolyLin[16];         /* end of aliased methods in array      -067f */
   311 } RivaLine;
   312 /*
   313  * 2D/3D surfaces
   314  */
   315 typedef volatile struct
   316 {
   317     U032 reserved00[4];
   318     U016 FifoFree;
   319     U016 Nop;
   320     U032 reserved01[0x0BE];
   321     U032 Offset;
   322 } RivaSurface;
   323 typedef volatile struct
   324 {
   325     U032 reserved00[4];
   326     U016 FifoFree;
   327     U016 Nop;
   328     U032 reserved01[0x0BD];
   329     U032 Pitch;
   330     U032 RenderBufferOffset;
   331     U032 ZBufferOffset;
   332 } RivaSurface3D;
   333 
   334 /***************************************************************************\
   335 *                                                                           *
   336 *                        Virtualized RIVA H/W interface.                    *
   337 *                                                                           *
   338 \***************************************************************************/
   339 
   340 struct _riva_hw_inst;
   341 struct _riva_hw_state;
   342 /*
   343  * Virtialized chip interface. Makes RIVA 128 and TNT look alike.
   344  */
   345 typedef struct _riva_hw_inst
   346 {
   347     /*
   348      * Chip specific settings.
   349      */
   350     U032 Architecture;
   351     U032 Version;
   352     U032 CrystalFreqKHz;
   353     U032 RamAmountKBytes;
   354     U032 MaxVClockFreqKHz;
   355     U032 RamBandwidthKBytesPerSec;
   356     U032 EnableIRQ;
   357     U032 IO;
   358     U032 VBlankBit;
   359     U032 FifoFreeCount;
   360     U032 FifoEmptyCount;
   361     /*
   362      * Non-FIFO registers.
   363      */
   364     volatile U032 *PCRTC;
   365     volatile U032 *PRAMDAC;
   366     volatile U032 *PFB;
   367     volatile U032 *PFIFO;
   368     volatile U032 *PGRAPH;
   369     volatile U032 *PEXTDEV;
   370     volatile U032 *PTIMER;
   371     volatile U032 *PMC;
   372     volatile U032 *PRAMIN;
   373     volatile U032 *FIFO;
   374     volatile U032 *CURSOR;
   375     volatile U032 *CURSORPOS;
   376     volatile U032 *VBLANKENABLE;
   377     volatile U032 *VBLANK;
   378     volatile U008 *PCIO;
   379     volatile U008 *PVIO;
   380     volatile U008 *PDIO;
   381     /*
   382      * Common chip functions.
   383      */
   384     int (*Busy) (struct _riva_hw_inst *);
   385     void (*CalcStateExt) (struct _riva_hw_inst *, struct _riva_hw_state *,
   386                           int, int, int, int, int, int, int, int, int, int,
   387                           int, int, int);
   388     void (*LoadStateExt) (struct _riva_hw_inst *, struct _riva_hw_state *);
   389     void (*UnloadStateExt) (struct _riva_hw_inst *, struct _riva_hw_state *);
   390     void (*SetStartAddress) (struct _riva_hw_inst *, U032);
   391     void (*SetSurfaces2D) (struct _riva_hw_inst *, U032, U032);
   392     void (*SetSurfaces3D) (struct _riva_hw_inst *, U032, U032);
   393     int (*ShowHideCursor) (struct _riva_hw_inst *, int);
   394     void (*LockUnlock) (struct _riva_hw_inst *, int);
   395     /*
   396      * Current extended mode settings.
   397      */
   398     struct _riva_hw_state *CurrentState;
   399     /*
   400      * FIFO registers.
   401      */
   402     RivaRop *Rop;
   403     RivaPattern *Patt;
   404     RivaClip *Clip;
   405     RivaPixmap *Pixmap;
   406     RivaScreenBlt *Blt;
   407     RivaBitmap *Bitmap;
   408     RivaLine *Line;
   409     RivaTexturedTriangle03 *Tri03;
   410     RivaTexturedTriangle05 *Tri05;
   411 } RIVA_HW_INST;
   412 /*
   413  * Extended mode state information.
   414  */
   415 typedef struct _riva_hw_state
   416 {
   417     U032 bpp;
   418     U032 width;
   419     U032 height;
   420     U032 repaint0;
   421     U032 repaint1;
   422     U032 screen;
   423     U032 pixel;
   424     U032 horiz;
   425     U032 arbitration0;
   426     U032 arbitration1;
   427     U032 vpll;
   428     U032 pllsel;
   429     U032 general;
   430     U032 config;
   431     U032 cursor0;
   432     U032 cursor1;
   433     U032 cursor2;
   434     U032 offset0;
   435     U032 offset1;
   436     U032 offset2;
   437     U032 offset3;
   438     U032 pitch0;
   439     U032 pitch1;
   440     U032 pitch2;
   441     U032 pitch3;
   442 } RIVA_HW_STATE;
   443 
   444 /*
   445  * FIFO Free Count. Should attempt to yield processor if RIVA is busy.
   446  */
   447 
   448 #define RIVA_FIFO_FREE(hwptr,cnt)                                  \
   449 {                                                                  \
   450    while (FifoFreeCount < (cnt))                                   \
   451 	FifoFreeCount = hwptr->FifoFree >> 2;                      \
   452    FifoFreeCount -= (cnt);                                         \
   453 }
   454 #endif /* __RIVA_HW_H__ */
   455 /* vi: set ts=4 sw=4 expandtab: */