include/SDL_atomic.h
changeset 7394 38dc4961ab15
parent 7393 358696c354a8
child 7677 871d43c6968a
equal deleted inserted replaced
7393:358696c354a8 7394:38dc4961ab15
   153  * single flag variable.
   153  * single flag variable.
   154  *
   154  *
   155  * For more information on these semantics, take a look at the blog post:
   155  * For more information on these semantics, take a look at the blog post:
   156  * http://preshing.com/20120913/acquire-and-release-semantics
   156  * http://preshing.com/20120913/acquire-and-release-semantics
   157  */
   157  */
   158 /* FIXME: This is correct for x86 and x64 but not other CPUs
   158 #if defined(__GNUC__) && (defined(__powerpc__) || defined(__ppc__))
   159    For PPC we need the lwsync instruction, and on ARM some variant of dmb
   159 #define SDL_MemoryBarrierRelease()   __asm__ __volatile__ ("lwsync" : : : "memory")
   160  */
   160 #define SDL_MemoryBarrierAcquire()   __asm__ __volatile__ ("lwsync" : : : "memory")
       
   161 #elif defined(__GNUC__) && defined(__arm__)
       
   162 #if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7S__)
       
   163 #define SDL_MemoryBarrierRelease()   __asm__ __volatile__ ("dmb ish" : : : "memory")
       
   164 #define SDL_MemoryBarrierAcquire()   __asm__ __volatile__ ("dmb ish" : : : "memory")
       
   165 #elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__)
       
   166 #ifdef __thumb__
       
   167 /* The mcr instruction isn't available in thumb mode, use real functions */
       
   168 extern DECLSPEC void SDLCALL SDL_MemoryBarrierRelease();
       
   169 extern DECLSPEC void SDLCALL SDL_MemoryBarrierAcquire();
       
   170 #else
       
   171 #define SDL_MemoryBarrierRelease()   __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" : : "r"(0) : "memory")
       
   172 #define SDL_MemoryBarrierAcquire()   __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" : : "r"(0) : "memory")
       
   173 #endif /* __thumb__ */
       
   174 #else
       
   175 #define SDL_MemoryBarrierRelease()   __asm__ __volatile__ ("" : : : "memory")
       
   176 #define SDL_MemoryBarrierAcquire()   __asm__ __volatile__ ("" : : : "memory")
       
   177 #endif /* __GNUC__ && __arm__ */
       
   178 #else
       
   179 /* This is correct for the x86 and x64 CPUs, and we'll expand this over time. */
   161 #define SDL_MemoryBarrierRelease()  SDL_CompilerBarrier()
   180 #define SDL_MemoryBarrierRelease()  SDL_CompilerBarrier()
   162 #define SDL_MemoryBarrierAcquire()  SDL_CompilerBarrier()
   181 #define SDL_MemoryBarrierAcquire()  SDL_CompilerBarrier()
       
   182 #endif
   163 
   183 
   164 
   184 
   165 /* Platform specific optimized versions of the atomic functions,
   185 /* Platform specific optimized versions of the atomic functions,
   166  * you can disable these by defining SDL_DISABLE_ATOMIC_INLINE
   186  * you can disable these by defining SDL_DISABLE_ATOMIC_INLINE
   167  */
   187  */